1. Field of the Invention
The present invention relates to a bus control device, and in particular to a bus control device which enables a plurality of devices such as processors and DMAC""s (Direct Memory Access Controllers) which can be a bus master to access a system bus.
In recent years, the performance of a serial processing computer is going to approach the physical limits. As one solution for further improving the performance of a computer, a multi-processor system has been proposed. In this system, how effectively the bus control device utilizes the system bus is important.
2. Description of the Related Art
FIG. 11 illustrates an arrangement of a general bus control device, in which to an address bus 21, a data bus 22, and a control bus 23 forming a system bus 20, are connected processors (hereinafter occasionally referred to as MPU""s) 10a and 10b, a DMAC 11, a memory 12, and processing circuits (hereinafter occasionally referred to as I/O""s (Input/Output circuits)) 13a and 13b. 
It is to be noted that FIG. 11 does not show a usual system bus controller for the MPU 10a, the MPU 10b, the DMAC 11, the memory 12, the I/O 13a, and the I/O 13b. 
FIG. 12 illustrates a timing sequence of the MPU 10a accessing the system bus 20, namely, a read cycle of the MPU 10a in which the MPU 10a reads data from the memory 12 and a write cycle in which the-MPU 10a writes data in the memory 12.
The bus control device in its entirety synchronizes with a bus clock 101, while the MPU 10a synchronizes with a clock 201 which is made by dividing the frequency of the bus clock 101 into the half.
In the read cycle, the MPU 10a outputs an address signal 202 at the fall of the clock 201 (at timing t41) and activates a memory read signal 203 (negative-true logic) at the subsequent rise of the clock 201 (at timing t42). A system bus controller of the MPU 10a, having received the address signal 202 and the memory read signal 203, activates an MPU 10a-bus request signal 102 (negative-true logic) at the subsequent rise of the bus clock 101 (at timing t43).
Upon receiving this request signal 102, the system bus first confirms that the address bus 21 and the data bus 22 are accessible, and then activates an MPU 10a-bus acknowledge signal 103 (negative-true logic) at the subsequent fall of the clock 101 (at timing t44). Having received this bus acknowledge signal 103, the system bus controller of the MPU 10a outputs the address signal 202 and the memory read signal 203 to the address bus 21 and the control bus 23 respectively.
Receiving the address signal 202 and the memory read signal 203 from the address bus 21 and the control bus 23 respectively, the memory 12 outputs a data signal 208 designated by the address signal 202 to the data bus 22. When the data signal 208 become effective on the data bus 22 (at timing t45), the system bus controller of the MPU 10a outputs a ready signal 207 notified by the memory 12 to the MPU 10a. The MPU 10a reads the data, completes the read cycle, and then releases the system bus (at timing t46).
In the write cycle, the MPU 10a outputs the address signal 202 at the fall of the clock 201 (at timing t51), and without activating the memory read signal 203, outputs a data signal (not shown in FIG. 12) at the subsequent rise of the clock 201 (at timing t52). As in the read cycle, the system bus controller of the MPU 10a, after having made a bus request with the bus request signal 102 (at timing t53), receives the bus acknowledge signal 103. Having received this bus acknowledge signal 103, the system bus controller outputs the address signal 202 to the address bus 21 and outputs the said data to the data bus 22 as the data bus signal 208.
The system bus controller of the MPU 10a outputs a memory write signal 204 to the control bus 23 (at timing t55). Having received this memory write signal 204, the memory 12 has the data signal 208 designated by the data bus 22 written in the address designated by the address signal 202 on the address bus 21. The system bus controller, after having completed writing data to the memory 12, outputs the ready signal 207 notified by the memory 12 to the MPU 10a (at timing t56). The MPU 10a completes the write cycle and releases the system bus (at timing t57).
FIG. 13 illustrates a timing sequence for the DMAC 11 to access the system bus 20, namely, a read and a write cycle for the DMAC 11 to read data from the memory 12 to write the data in the I/O 13a and to write the data read from the I/O 13a in the memory 12, respectively.
As in FIG. 12, the bus control device in its entirety synchronizes with the bus clock 101, while the DMAC 11 synchronizes with the clock 201 which is made by dividing the frequency of the bus clock 101 into the half.
In the read cycle, the DMAC 11 outputs the address signal 202 at the fall of the clock 201 (at timing t61) and activates-the memory read signal 203 (negative-true logic) at the ;subsequent rise of the clock 201 (at timing t62). A system bus controller of the DMAC 11 transmits/receives a DMAC-bus request signal 102 (hereinafter a hyphen xe2x80x9c-xe2x80x9d indicates that the latter is used for the former) and a DMAC-bus acknowledge signal 103 to/from the system bus, and acquires a use (right for use) of the system bus (at timings t63, t64). Then the system bus controller of the DMAC 11 outputs the address signal 202 and the memory read signal 203 to the address bus 21 and the control bus 23 respectively.
Receiving the address signal 202 and the memory read signal 203 from the address bus 21 and the control bus 23 respectively, the memory 12 outputs the data signal 208 designated by the address signal 202 to he data bus 22. At the subsequent rise of the clock 201 (at timing t65), he DMAC 11 outputs an I/O write signal 206.
When the data signal 208 become effective on the data bus 22, the I/O 13a, having received the I/O write signal 206, reads the data signal 202 on the data bus 22. The system bus controller of the DMAC 11 outputs the ready signal 207 notified by the memory 12 (at timing t66). The DMAC 11 completes the read cycle and releases the system bus (at timing t67).
In the write cycle, the operations at the timings t71xcx9ct74 are the same as the read cycle except that at at timing t72, the DMAC 11 activates an I/O read signal 205 instead of activating the memory read signal 203. At timing t74, having acquired a use of the system bus, the system bus controller of the DMAC 11 outputs the address signal 202 and the I/O read signal 205 to the address bus 21 and the data bus 23, respectively.
Upon receiving the I/O read signal 205, the I/O 13a outputs the data signal 208 to the data bus 22. At the subsequent rise of the clock 201 (at timing t75), the DMAC 11 outputs a memory write signal 204. In response to this signal, the memory 12 has the address signal 202 on the address bus 21 to read in the data signal 208 on the data bus 23.
At the end of the reading operation in view of the memory access time (at timing t76), the system bus controller of the DMAC 11 outputs the ready signal 207 notified by the memory 12 to the DMAC 11. Then the DMAC 11 completes the write cycle and releases the system bus (at timing t77).
In such a prior art bus control device, any one of the MPU 10a, the MPU 10b and the DMAC 11 executes the process as a bus master. This bus master occupies the system bus 20 from the beginning to the end of the cycle time for accessing the memory 12 or the I/O""s 13a, 13b. 
Therefore, the MPU or the DMAC other than the bus master has to wait until the bus master completes the cycle time and releases the system bus 20 because no acknowledge signal is returned for the bus request signal.
As a result, even if a plurality of MPU""s or DMAC""s are mounted in order to improve the performance of a system, due to a bottleneck caused by the system bus 20, the performance of the entire system is restricted to the extent of 50 to 60% at most by the multiple of the increased number of devices such as MPU""s. Moreover, if the access time of the memory 12, the I/O 13a, or the I/O 13b is short, the system bus 20 is occupied by the memory 12, the I/O 13a, or the I/O 13b, resulting in a decline of the entire system performance.
For the solution, there is a method in which priorities are assigned to the bus accesses by a plurality of MPU""s and DMAC""s, accepting the bus request from an MPU or a DMAC in the order of the priority to shorten the waiting time. Usually, the priority for the bus access is assigned higher for the DMAC than the MPU. In this case, when the DMAC begins the data transfer, the MPU has to wait until all the data transfer by the DMAC is finished. Therefore, the MPU of the bus control device including the DMAC is not applicable to a system requiring a real time processing. For the measures, the MPU""s and the DMAC""s may use different buses. However, this requires a large-scaled system and a high cost.
In addition, if the MPU 10a hangs up while occupying the system bus 20, the other MPU 10b and the DMAC11 cannot access the system bus 20 so that the system is shut down, thereby disabling the restoration.
As an art dealing with this problem, the Japanese Patent Laid-Open No. 60-147866 discloses a multi-processor system in which data transfer is made between an MPU which has acquired a use of a bus as a bus master and an associated MPU as a bus slave. In this system, the bus master, without waiting for a ready signal from the bus slave, completes the bus access cycle in a certain period of time. If an XACK signal indicates that the data transfer is completed, the bus master completes the processor cycle. If the XACK signal indicates that the data transfer is incomplete, the bus master repeats the access to the bus slave through the bus in order to enable the data transfer.
Thus, even if the aforementioned hang-up state occurs, the system bus is once released, so that the system can continue the process without shutdown.
However, in this known example, if the XACK signal indicates that the data transfer is incomplete, the bus master repeatedly accesses the bus slave through the system bus until the data transfer is completed. This increases the time for which the system bus is being occupied, and worsens the efficiency of the bus utilization. Moreover, since the bus master accesses the system bus at the same timing as the cycle timing of the bus master, this example has not solved the decrease in the performance of the entire system due to the bottleneck caused by the system bus.
As an art dealing with this bottleneck, the Japanese Patent Laid-Open No. 5-265932 discloses a multi-processor system that controls a system bus with a common bus controller, in which an interface having a storage unit and a controller are connected between each MPU and the system bus. In this system, a memory with an access speed higher than each MPU is connected to the system bus. Data transfer between the MPU and the storage unit of the interface is done at an MPU access speed, so that a high-speed data transfer between the storage unit and the memory is achieved.
In this known example, the access time of the system bus depends on that of the memory. Therefore, it is always necessary to use a memory of a speed higher than the access time of the MPU, so that a cheap and high-capacity memory such as DRAM cannot be used.
It is accordingly an object of the present invention to provide a bus control device having a plurality of devices such as MPU""s and DMAC""s which can be a bus master are able to access a system bus wherein a system bus is efficiently used without the use of an expensive high-speed device or without being influenced by a low-speed device.
[1] For the achievement of the above-mentioned object, in a bus control device according to the present invention in which an MPU (processor) 10a which is a bus master and a memory 12 are commonly connected to a system bus, as schematically shown in FIG. 1, an MPU10 output buffer 30 is provided between the MPU 10a and the system bus 20. An MPU-system bus controller 15 controls the output buffer 30 with an output enable signal 40 (41), whereby an address signal 202, a control signal 24xe2x80x2 and a data signal 208, which are output signals of the MPU 10a, access the system bus 20 within the accessible minimum time as an address signal 21 which also designates an address bus 21, a system control signal 24 and a data signal 22 which also designate a data bus 22, respectively.
As schematically shown in FIG. 2, a memory-latch circuit 33 is provided between the system bus 20 and the memory 12. A memory-system bus controller 16 controls the input timing of the latch circuit 33 with a latch enable signal 51, whereby the address signal 21, the data signal 22 and the system control signal 24, which are the output signals on the system bus 20, are stored and converted into an address signal 121, a data signal 122, a chip select signal 53 and a write signal 124, which are write signals for the memory 12, when the said output signals indicate the. memory write signals.
As a result, the time for the MPU 10a and the memory 12 accessing the system bus 20 can be minimized. Within this accessible minimum time, the MPU 10a will be able to write designated data in designated addresses on the memory 12.
It is to be noted that although an MPU-system bus synchronization controller 32 in FIG. 1 is included in the system bus controller 15, and a memory-control timing generator 34 in FIG. 2 is included in the system bus controller 16, they are shown outside of the system bus controllers 15, 16.
[2] Also, this invention, in addition to the above bus control device [1], comprises a memory output buffer 35 between the memory 12 and the system bus 20 (see FIG. 2) and an MPU latch circuit 31 between the system bus 20 and the MPU 10a (see FIG. 1). When the control signal 24 in FIG. 2, which forms the said output signals, indicates a memory read signal, the memory-system bus controller 16 converts it into a read signal in consideration of the access time of the memory 12, and when the output data signal 122 of the memory 12 becomes stable by controlling the memory output buffer 35, accesses the system bus 20 with the output data signal 22 within the accessible minimum time.
As illustrated in FIG. 1, the MPU-system bus controller 15 controls the input timing of the MPU latch circuit 31 with a system bus access/read signal 44 and a latch timing signal 46, thereby storing the data signal 22 to be read in the MPU 10a as the data signal 208.
As a result, the time for the MPU 10 and the memory 12 to access the system bus 20 can be minimized. Within this accessible minimum time, the MPU 10a will be able to read the data from the designated address on the memory 12.
[3] This invention will be described referring to FIG. 2 to 4.
The DMAC 11, which is a bus master (see FIG. 3), the memory 12 (see FIG. 2) and the processing circuit I/O 13a (see FIG. 4) are commonly connected to the system bus 20. A DMAC output buffer 36 (see FIG. 3) is provided between the DMAC 11 and the system bus 20.
As illustrated in FIG. 3, a DMAC-system bus controller 17 controls the output buffer 36 with an output enable signal 60, so that an address signal 202, the control signal 24xe2x80x2 and a DMAC control signal 26, which are the output signals of the DMAC 11, may access the said system bus as the address signal 21, the system control signal 24 and the DMAC control signal 26, respectively within the accessible minimum time.
As illustrated in FIG. 2, similar to the above [1] and [2], the memory latch circuit 33 is provided between the system bus 20 and the memory 12. The memory-system bus controller 16 controls the memory latch circuit 33 with the latch enable signal 51, thereby latching the address signal 21, the data signal 22, the system control signal 24, and the bus control signal 25 which are the output signals on the system bus 20.
When the said output signal indicates a memory read signal, the memory-system bus controller 17 converts the said output signal into an address signal 121 which is a read signal in consideration of the access time of the memory 12 and the chip select signal 53. When the output data signal 122 of the memory 12 becomes stable, the controller 17 transmits the output data signal 122 through the output buffer 35 to the system bus 20 as the data signal 22 within the accessible minimum time.
As illustrated in FIG. 4, an I/O-system bus controller 18 which is the system bus controller for the processing circuit writes the data signal 22 in the processing circuit i.e. I/O 13a with signals 72 and 73 when the address signal 21, the data signal 22 and the system control signal 24, which are the output signals from the system bus 20, indicate data write signals.
As a result, the time for the DMAC 11, the memory 12 and the I/O 13a to access the system bus 20 can be minimized. Within this accessible minimum time, the DMAC 11 will be able to read the data from the designated address on the memory 12 and write the data in the designated I/O 13a. 
It is to be noted that although a DMAC-system bus synchronization controller 37 in FIG. 3 is included in the system bus controller 17 and an I/O-control timing generator 38 in FIG. 4 is included in the system bus controller 18, they are shown outside of the system bus controllers 17, 18.
[4] This invention will be described referring to FIG. 2 to 4.
Similar to the above [3], the DMAC 11, the memory 12 and the I/O 13a are commonly connected to the system bus 20, and the DMAC output buffer 36 (see FIG. 3) is provided between the DMAC 11 and the system bus 20.
As illustrated in FIG. 3, the DMAC-system bus controller 17 controls the output buffer 36 with the output enable signal 60, and using the address signal 202, the control signal 24xe2x80x2 (203xcx9c206) and the DMAC control signal 26, which are the output signals of the DMAC 11, access the system bus on the address signal 21, the system control signal 24 and the DMAC control signal 26 within the accessible minimum time.
As illustrated in FIG. 4, an I/O-output buffer 39 is provided between the I/O 13a and the system bus 20. When the control signal 24 which is the output signal indicates an I/O readout, by controlling the output buffer 39 with an output enable signal 71 the I/O-system bus controller 18 transmits the data signal 22 which is the output data of the I/O 13a to the system bus 20 within the accessible minimum time.
As illustrated in FIG. 2, similar to the above, the memory latch circuit 33 is provided between the system bus 20 and the memory 12. The memory-system bus controller 16 controls the memory latch circuit 33 with the latch enable signal 51, whereby the address signal 21, the data signal 22 and the system control signal 24, which are the output signals on the system bus 20, are stored and converted into the address signal 121, the system control signal 23xe2x80x2, the data signal 122, the chip select signal 53 and the write signal 124, which are write signals in consideration of the access time of the memory 12.
As a result, the time for the DMAC 11, the memory 12 and the I/O 13a to access the system bus 20 can be minimized. Within this accessible minimum time, the DMAC 11 will be able to read the data from the designated I/O 13a and write the data in the designated memory 12.
[5] This invention will be described referring to FIGS. 1 and 4.
The MPU (processor) 10a (see FIG. 1) and the I/O 13a (see FIG. 4) are commonly connected to the system bus 20.
In FIG. 1, as above mentioned, the MPU-output buffer 30 is provided between the MPU 10a and the system bus 20. The MPU-system bus controller 15 controls the output buffer 30 with the output enable signal 40 (41), whereby the address signal 202, the control signal 24xe2x80x2 and the data signal 208, which are output signals of the MPU 10a, access the system bus 20 as the address signal 21, the system control signal 24 and the data signal 22, respectively within the accessible minimum time.
In FIG. 4, when the address signal 21, the data signal 22 and the system control signal 24, which are the output signals on the system bus 20, indicate I/O write signals, the I/O-system bus controller 18 converts the said output signals into write signals to output the chip select signal 72 and the write signal 73 for writing the data.
As a result, the time for the MPU 10a and the I/O 13a to access the system bus 20 can be minimized. Within this accessible minimum time, the MPU 10a will be able to write the data in the designated I/O 13a. 
[6] This invention will be described referring to FIGS. 1 and 4.
As above mentioned, the MPU (processor) 10a and the I/O 13a are commonly connected to the system bus 20.
In FIG. 4, the I/O-output buffer 39 is provided between the I/O 13a and the system bus 20, and by controlling the output buffer 39 with the output enable signal 71 the I/O-system bus controller 18 transmits the data signal 22 which is the output data of the I/O 13a to the system bus 20 within the accessible minimum time.
In FIG. 1, as above mentioned, the MPU latch circuit 31 is provided between the system bus 20 and the MPU 10a, and the MPU-system bus controller 15 controls the MPU latch circuit 31 with the system bus access/read signal 44 and a latch timing signal 46, thereby having the MPU 10a read in the output data 22 on the system bus 20 as the data signal 208.
As a result, the time for the MPU 10a and the I/O 13a to access the system bus 20 can be minimized. Within this accessible minimum time, the MPU 10a will be able to read the data from the designated address on the I/O 13a. 
[7] Also, this invention, in addition to the above bus control device [3] or [5], as in the case with the memory latch circuit 33 shown in FIG. 2, an I/O latch circuit is provided. The I/O-system bus controller 18 controls the I/O latch circuit 33, whereby the address signal 21, the data signal 22 and the system control signal 23, which are the output signals on the system bus 20, are temporarily stored and converted into write signals in consideration of the access time of the I/O 13a. 
As a result, the I/O 13a can definitely read in the data according to the access time.
[8] In addition, this invention, in any one of the above bus control devices [1] to [6], when a bus master of the system bus 20 has not completed the cycle and not accessed the system bus 20, another bus master may access the said system bus.
Namely, if a plurality of devices which can be a bus master are commonly connected to the system bus, when the device which is the bus master temporarily releases the system bus in a read/write cycle for instance, another device can use the system bus by performing a bus request.
As a result, since each bus master can use the system bus with a minimum occupation time, another bus master can use the released time of the system bus, thereby improving the utilization efficiency of the system bus.
[9] Also, in this invention, the processor, the memory, the DMAC and the I/O in the above bus control device [7] can be a bus master.
[10] Also, in this invention, the said memory latch circuit in any one of the above bus control devices [1], [3] and [4] may be a FIFO.
In FIG. 2, when the access time of the memory 12 is short, a FIFO is used for the latch circuit 33. As a result, the action for which each bus master access can be maintained.